The present invention relates to a semiconductor design technology, and more particularly, to an output enable signal generator for use in a semiconductor memory device.
An output enable signal generator included in a synchronous dynamic random access memory (SDRAM) is used in order to output a data satisfying a corresponding CAS latency (CL) in response to a read command.
FIG. 1 is a block diagram depicting a conventional output enable signal generator.
As shown, the conventional output enable signal generator includes a delayed locked loop (DLL) clock count unit 10 for counting a DLL clock RCLKDLL in response to a clock enable signal CKE, an external clock count unit 11 for counting an external clock EXTCLK, a comparison unit 12 for comparing an output of the DLL clock count unit 10 with an output of the external clock count unit 11 in response to a read command RD, and an output enable signal generation unit 13 for generating an output enable signal OUTEN by using a latency signal LATENCY output from the comparison unit 12.
Further, the conventional output enable signal generator includes a count control unit 14 for enabling and disabling the DLL clock count unit 10 and the external clock count unit 11 in response to an output enable signal reset signal OERESET.
Herein, the comparison unit 12 and the output enable signal generation unit 13 are synchronized with the DLL clock RCLKDLL.
FIG. 2 is a block diagram illustrating the conventional output enable signal generator shown in FIG. 1 in detail.
As shown, the DLL count unit 10 includes an initialization unit 20, a signal generation unit 21 and a DLL clock count circuit 22.
The signal generation unit 21 serves to generate a DLL clock enable signal RCLKDLLCKE which corresponds to the clock enable signal CKE. That is, the signal generation unit 21 generates the DLL clock enable signal RCLKDLLCKE in response to the DLL clock RCLKDLL and the clock enable signal CKE.
In detail, the signal generation unit 21 includes a first D flip-flop DFF1 for transferring the clock enable signal CKE by receiving the DLL clock RCLKDLL as a control signal and a first AND gate AND1 for receiving an output signal CKEDLL of the first D flip-flop DFF1 and the DLL clock RCLKDLL in order to generate the DLL clock enable signal RCLKDLLCKE which corresponds to the clock enable signal CKE.
The initialization unit 20 serves to initialize the DLL clock count circuit 22. The initialization unit 20 receives a CAS latency CL<5:11> and calculates a formula ‘16-(CL-3)’ using a value of the received CAS latency in order to set the DLL clock count circuit 22. Herein, the CAS latency CL<5:11> is set by a mode register set (MRS). Further, ‘16’ of the formula ‘16-(CL-3)’ is due to a 16-bit system of the DLL clock count circuit 22, and ‘3’ is for securing a cross margin between the external clock EXTCLK and the DLL clock RCLKDLL.
The DLL clock count circuit 22 is set by the initialization unit 20 and serves to count the DLL clock enable signal RCLKDLLCKE.
The external clock count unit 11 includes a signal generation unit 31 and an external clock count circuit 32.
The signal generation unit 31 serves to generate an external clock enable signal EXTCLKCKE which corresponds to the clock enable signal CKE. In response to the external clock EXTCLK and the clock enable signal CKE, the signal generation unit 31 generates the external clock enable signal EXTCLKCKE.
In detail, the signal generation unit 31 includes a second D flip-flop DFF2 for transferring the clock enable signal CKE by receiving the external clock EXTCLK as a control signal, and a second AND gate AND2 for receiving an output signal CKEEXT of the second D flip-flop DFF2 and the external clock EXTCLK in order to generate the external clock enable signal EXTCLKCKE which corresponds to the clock enable signal CKE.
The external clock count circuit 32 serves to count the external clock enable signal EXTCLKCKE.
The comparison unit 12 stores an external clock count signal group EXTCNT<3:0> output from the external clock count circuit 32 in response to a read command RD and compares the stored signal group with a DLL clock count signal group DLLCNT<3:0> output from the DLL clock count circuit 22. When the external clock count signal group EXTCNT<3:0> has the same value as that of the DLL clock count signal group DLLCNT<3:0>, the comparison unit 12 outputs the latency signal LATENCY.
The output enable signal generation unit 13 includes a delay circuit 41 for delaying the latency signal LATENCY output from the comparison unit 12 and a signal generation unit 42 for generating the output enable signal OUTEN in response to an output of the delay circuit 41.
Herein, the delay circuit 41 has a delay amount for securing an output margin of the latency signal LATENCY which is delayed for an internal delay amount before it is outputted as the output enable signal OUTEN.
The count control unit 14 includes a third D flip-flop DFF3 for transferring the output enable reset signal OERESET by receiving the DLL clock RCLKDLL as a control signal, a delay unit 51 for delaying an output signal of the third D flip-flop DFF3 for a predetermined delay amount tDLL, and a fourth D flip-flop for transferring an output signal of the delay unit 51 by receiving the external clock EXTCLK as a control signal.
FIGS. 3A and 3B are timing diagrams showing an operation of the conventional output enable signal generator shown in FIGS. 1 and 2.
Referring to FIG. 3A, a semiconductor memory device is normally operated as follows. The external clock count circuit 32 begins to perform a count operation in response to an inactivation of a delayed output enable reset signal OERESETEXT generated by delaying the output enable reset signal OERESET for the DLL time tDLL, i.e., the delay amount of a delay model of a DLL. At this time, the DLL clock count circuit 22 is performing a count operation by the initialization unit 20.
Thereafter, the read command RD is inputted and an external clock count value (3) is stored. When a DLL clock count value (3) equals the external clock count value (3), the comparison unit 12 outputs the latency signal LATENCY.
By using the latency signal LATENCY, the output enable signal OUTEN is generated, and read data D0 to D7 are outputted in response to the output enable signal OUTEN.
However, according to the operation of the conventional output enable signal generator, the DLL clock count circuit 22 and the external clock count circuit 32 need not be operating in an active power down mode. In the active power down mode, a column enable transistor YI, which serves to connect a bit line to a segment input/output line (SIO), is not operated when a word line and a bit line are enabled.
That is, by stopping operations of the DLL clock count circuit 22 and the external clock count circuit 32, power consumption can be reduced.
However, in accordance with the conventional output enable signal generator, when the operations of the DLL clock count circuit 22 and the external clock count circuit 32 are stopped in the active power down mode, a problem occurs as follows.
FIG. 3B shows an abnormal operation of the conventional output enable signal generator when the DLL clock count circuit 22 and the external clock count circuit 32 are disabled during the active power down mode.
As shown, when the semiconductor memory device enters the active power down mode, an internal clock enable signal INTERNALCKE is activated. Further, the operations of the DLL clock count circuit 22 and the external clock count circuit 32 are stopped during an inactive period of the internal clock enable signal.
That is, during the inactive period of the internal clock enable signal, by stopping the toggling of the external clock enable signal EXTCLKCKE and the DLL clock enable signal RCLKDLLCKE, the operations of the DLL clock count circuit 22 and the external clock count circuit 32 are stopped.
However, if the DLL clock count signal DLLCNT is inactivated, activation timing of the DLL clock RCLKDLL becomes different from that of the normal operation mode in terms of frequency. This means that an enabling timing of the DLL clock count unit 10 is changed.
Although data is transferred in the semiconductor memory device in synchronization with the DLL clock RCLKDLL, which is an internal clock, before the data is output from the semiconductor memory device, the data is finally transferred to the outside in synchronization with the external clock EXTCLK. Therefore, the DLL clock should lead the external clock EXTCLK.
As shown in FIG. 3B, since the external clock EXTCLK and the DLL clock RCLKDLL begin to toggle almost at the same time in response to an activation of the internal clock enable signal INTERNALCKE, if the read command RD is inputted after completing the active power down mode, output data DQ, which are output, are delayed by one clock relative to the expected CL.